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R
LCD Controller
Table 5-2:
LCD Character Display Command Set (4-bit mode) (Continued)
Function
Upper Nibble
Lower Nibble
Function Set
Set CG RAM Address
Set DD RAM Address
Read Busy Flag and Address
Write Data to CG RAM or DD RAM
Read Data from CG RAM or DD RAM
0
0
0
0
1
1
0
0
0
1
0
1
0
0
1
BF
D7
D7
0
1
A6
A6
D6
D6
1
A5
A5
A5
D5
D5
0
A4
A4
A4
D4
D4
1
A3
A3
A3
D3
D3
0
A2
A2
A2
D2
D2
-
A1
A1
A1
D1
D1
-
A0
A0
A0
D0
D0
Disabled
If the LCD_E enable signal is Low, all other inputs to the LCD are ignored.
Clear Display
Clears the display and returns the cursor to the home position, the top-left corner.
This command writes a blank space (ASCII/ANSI character code 0x20) into all DD RAM
addresses. The address counter is reset to 0, location 0x00 in DD RAM. Clears all option
settings. The I/D control bit is set to 1 (increment address counter mode) in the Entry Mode
Set command.
Execution Time: 82 μ s – 1.64 ms
Return Cursor Home
Returns the cursor to the home position, the top-left corner. DD RAM contents are
unaffected. Also returns the display being shifted to the original position, shown in
Figure 5-3 .
The address counter is reset to 0, location 0x00 in DD RAM. The display is returned to its
original status if it was shifted. The cursor or blink move to the top-left character location.
Execution Time: 40 μ s – 1.6 ms
Entry Mode Set
Sets the cursor move direction and specifies whether or not to shift the display.
These operations are performed during data reads and writes.
Execution Time: 40 μ s
Bit DB1: (I/D) Increment/Decrement
0
1
Auto-decrement address counter. Cursor/blink moves to left.
Auto-increment address counter. Cursor/blink moves to right.
This bit either auto-increments or auto-decrements the DD RAM and CG RAM address
counter by one location after each Write Data to CG RAM or DD RAM command or Read
Spartan-3A/3AN FPGA Starter Kit Board User Guide www.xilinx.com
UG334 (v1.1) June 19, 2008
49
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